1. Field of the Invention
This invention relates generally to fabrication of integrated circuits, and more particularly to controlling the channel length of transistors by laterally diffusing a nitrogen implant.
2. Description of the Related Art
MOSFETs (metal-oxide-semiconductor-field-effect transistors) are the basic building blocks of modern integrated circuits. The conventional fabrication of MOSFET devices is well known. Typically, MOSFETs are manufactured by depositing an undoped polycrystalline silicon ("polysilicon") material over a relatively thin gate oxide arranged above a semiconductor substrate. The polysilicon material and the gate oxide are patterned to form a gate conductor arranged between a source region and a drain region. The gate conductor and source/drain regions are then implanted with an impurity dopant. If the dopant species employed for forming the source/drain regions is n-type, then the resulting MOSFET is an NMOSFET (n-channel) transistor device. Conversely, if the source/drain dopant species is p-type, then the resulting MOSFET is a PMOSFET (p-channel) transistor device. Integrated circuits utilize either n-channel devices exclusively, p-channel devices exclusively, or a combination of both on a single monolithic substrate.
The dimensions of MOSFETs play a critical role in determining the speed and complexity of integrated circuits. The complexity of an integrated circuit is a function of the number of MOSFETs that can be packed into a given substrate area. Clearly, reducing the lateral width of the gate conductor will translate into an increased transistor surface density. Decreasing the width of the gate conductor, and hence the channel length also reduces the transistor threshold voltage, V.sub.T, which in turn leads to faster integrated circuits. Several factors contribute to V.sub.T, one of which is the effective channel length ("L.sub.eff ") of the transistor. The initial distance between the source and the drain of a transistor is often referred to as the physical channel length. However, after implantation and subsequent diffusion of the source/drain regions, the actual distance between the source and drain becomes less than the physical channel length and is often referred to as the effective channel length, L.sub.eff. In VLSI designs, as the physical channel length decreases, so too must L.sub.eff. Decreasing L.sub.eff reduces the distance between the depletion regions associated with the source and drain of a transistor. As a result, less gate charge is required to invert the channel of a transistor having a shorter L.sub.eff. Accordingly, reducing the physical channel length, and hence the L.sub.eff, can lead to a reduction in the threshold voltage of a transistor. Consequently, the switching speed of the logic gates of an integrated circuit employing transistors with reduced L.sub.eff is faster, allowing the integrated circuit to quickly transition between logic states (i.e., operate at high frequencies).
Minimization of the physical channel length of a transistor is limited by conventional techniques used to define the gate conductor of the transistor. As transistor geometries shrink below 0.5 micron, the limitations of conventional transistor processing become more and more apparent. As previously indicated, gate conductors are typically formed from polysilicon. A technique known as optical lithography, or photolithography, is used to pattern a photosensitive film (i.e., photoresist) formed above the polysilicon material. According to this technique, an optical image is transferred to the photoresist by projecting electromagnetic radiation, typically ultraviolet light, through the transparent portions of a mask plate. The solubility of photoresist regions exposed to the radiation is altered by a photochemical reaction. The photoresist is washed with a solvent that preferentially removes the altered resist areas of higher solubility. Exposed portions of the polysilicon material not protected by photoresist are etched away, defining the geometric shape of a polysilicon gate conductor.
The lateral width (i.e., the distance between opposed sidewall surfaces) of the gate conductor, which dictates the physical channel length of a transistor, is thus defined by the lateral width of an overlying photoresist layer. The minimum lateral dimension that can be achieved for a patterned photoresist layer is unfortunately limited by the resolution of the optical system (i.e., aligner or printer) used to project the image onto the photoresist. The term "resolution" describes the ability of an optical system to distinguish closely spaced objects.
Resolution in photolithography systems is limited by diffraction effects, which spread radiation from the illumination source into regions of the photoresist which are not directly exposed to the illumination source. Because of diffraction effects, there is a minimum distance beyond which even a geometrically perfect lens cannot resolve two points. In other words, when two points are less than a minimum distance from each other, the two points cannot be resolved by the lithography system. The diffraction patterns associated with each point overlap each other to such an extent that the two points cannot be effectively differentiated. The resolution of a lens depends on the wavelength of the illumination source and the numerical aperture of the lens. Rayleigh's criteria defines two images as being resolvable when the intensity between them drops to 80% of the image intensity. This criteria is satisfied when 2d=0.61.lambda./NA, where 2d is the distance separating two images, .lambda. is the wavelength of the radiation, and NA is the numerical aperture of the lens. Thus, for a given photolithography system, Rayleigh's criteria predicts a threshold. Beyond this photolithography threshold, the features patterned upon a masking plate may be skewed, enlarged, shortened, or otherwise incorrectly printed onto the photoresist.
It would be advantageous to develop a technique for manufacturing a transistor in which the channel length of the transistor is reduced to provide for high-frequency operation of an integrated circuit employing the transistor. More specifically, a process is needed in which the lateral width of the gate conductor and underlying channel length are no longer dictated by the resolution of photolithography systems.